One of the most important development aims in the field of memory cells is the realization of increasingly smaller memory cells, i.e., the use of increasingly smaller chip areas per bit stored. Up to now, it has been considered advantageous to realize compact cells by means of buried, i.e., diffused bit lines. However, bit lines implemented as diffusion areas become increasingly highly resistive as their structural size decreases, since the diffusion depth must be scaled as well, so as to counteract the risk of a punch through between neighboring bit lines. The problem arising in this connection is that high-resistance bit lines permit only comparatively small cell blocks so that the utilization degree decreases and the advantage of the smaller memory cells, for which a higher process expenditure must be tolerated, diminishes.
One example of known memory cells with buried bit lines and a virtual-ground-NOR architecture is described in the article: “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, Boaz Eitan et al, IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, which article is incorporated herein by reference. These concepts increase the resolution capabilities in semiconductor manufacturing. However, significant efforts and investments are needed to produce memories having the best possible resolution capabilities.
A further example of known memory cells is described in U.S. Pat. No. 6,686,242, which is incorporated herein by reference. A method for producing bit lines for a memory cell array comprises as a first providing a layer structure with a substrate having transistor wells implanted in a surface thereof. A sequence of storage medium layers is provided on the surface of the substrate, and a gate region layer is provided on the sequence of storage medium layers. Bit line recesses, which extend down to the sequence of storage medium layers, are produced in the gate region layer. Subsequently, insulating spacer layers are produced on lateral surfaces of the bit line recesses, whereupon a source/drain implantation is executed in the area of the bit line recesses, after a complete or partial removal of the sequence of storage medium layers.
Following this, the substrate is exposed completely in the area of the bit line recesses, if this has not yet been done prior to the implantation. Subsequently, metallization for producing metallic bit lines are produced on the exposed substrate. The metallization is insulated from the gate region layer by the insulating spacer layers.